DFT and Design Engineer Intern

Ambarella Highlands-Baywood Park, CA 2019-07-02

Position Responsibilities:

  • Logic Design to support DFT features
  • Automate DFT Flows (Scan, Compression & MBIST) used for complex multi-million gate SoC
  • Verification of DFT Logic and analysis of fault coverage
  • Timing analysis for DFT Modes

Minimum Requirements:

  • MSEE in Electrical / Computer Engineering
  • Knowledge of DFT fundamentals
  • Knowledge of Logic design & Static timing analysis
  • Knowledge of Verilog and any scripting language
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